The MS8702 Project

A highly scalable distributed memory parallel machine, the MS8702 was designed to experiment with massive parallelism. It can be considered a low cost prototype of the design proposed in 1991 with the i860 CPU replaced with a 68020+68881 16 MHz combination and the custom communication chip replaced with a T222 16 bit transputer. The FIFOs for interfacing the communications chip were replaced by shared memory to reduce costs. On the other hand, I/O was enhanced with an additional bus connecting the nodes directly to the PC AT host, as proposed by Sergio Takeo Kofuji. This allows node communication and I/O to be studied separately.

Each node is connected to its four neighbors simply by being inserted into the backplane. A 16 node rack forms a 4 x 4 mesh. The edge connections are converted to differential signals and can go to another rack using a 16 wire cable. The prototype's cabinet holds the host and four racks for a 64 node configuration. This can be easily expanded if needed.

see also:
| merlin | | jecel | | ms8702 | | sinde |
back to:
| LSI | | USP |
please send comments to jecel@lsi.usp.br (Jecel Mattos de Assumpcao Jr), who changed this page on Jun 29, 17:08 .