The SINDE Project
In August, 1982 the Laboratorio de Sistemas Integrados
at the University of Sao Paulo needed serious
computing power for VLSI CAD and process simulations.
It already had developed graphic terminals, so a group
was set up to integrate commercial VERSAmodules with
Motorola's VERSADos real time operating system.
By early 1983, however, it was decided that ( given the
Lab's resources and cost structure ) it would be
cheaper to design the whole machine in-house. Jecel
Assumpcao Jr headed the hardware design while Osvaldo
Cristo was in charge of the OS. Jecel's micro background
and Osvaldo's knowledge of mainframes combined with a
few ideas inspired by Intel's iAPX432 architecture resulting
in an interesting design.
Both symmetric and asymmetric multiprocessing were used to
achieve scalable performance. The highly modular design also reflected
the move to the smaller VERSAmodule European ( VME ) form
and the low density logic then available. VME's arbitration logic
was enhanced to allow a greater number of bus masters ( it
ended up looking like what NuBus or FutureBus use ). A SINDE
computer was to be built from one or more of each of these
modules:
General Purpose Processor
Includes a 68010 CPU and a
combination MMU/16KB cache memory. A local timer and ROMs
allow the OS kernel and time slice mechanism to operate without
using up VMEbus bandwidth. A single word write buffer also
improves performance.
Memory
Any VMEbus memory module should work, but the
first design used static memory for simplicity.
Character I/O
The 68000 processor has its own local
memory and timer. Part of the CPU bus was extended to a
remote enclosure using a shielded flat cable with differential
signal. This enclosure could accept up to 16 simple parallel
or serial interface boards ( several type could be designed,
such as RS232, RS422 or current loop ).
Block I/O
Very similar to the character I/O with a
68000 and RAM and a single SCSI interface. This module was
to be designed last as SCSI was still being defined at the
time.
Notable for their absence are system-wide interrupts. All
communication between processes or processors was via
messages. As processes lacked shared memory, there was
no cache coherency hardware ( the ready queues and message
queues were in non-cachable memory regions ).
The bulk of what is normally the OS ran as regular processes
in the GPPs, while the low level I/O ran as "embedded"
processes on the character and block I/O boards.
Besides the message passing micro-kernel parts of the OS
design, several features predated their popularization in
other projects:
- Unix source compatible
- shared libraries
- memory mapped files
Simulations showed that three or four GPPs would be the
practical limit, but some configurations might prefer to
beef up the I/O instead.
In late 1984, the project changed as financial backing from
Prologica made fast results a priority and the original
designers moved on to projects outside LSI. Three generations
of uniprocessor Unix-clone boxes followed, with the multiprocessing
theme fully explored in the 1987 MS8701 hierarchical, shared
memory project.
see also:
| ms8702 |
| sinde |
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please send comments to jecel@lsi.usp.br
(Jecel Mattos de Assumpcao Jr), who changed this page on
Jun 29, 17:08
.